kumoh national institute of technology
Networked Systems Lab.

Review Comment

NSL > Education> Review Comment
Seung-Han - ETFA 2017
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Date : 2017-06-18
Views : 221

Review 1
Overall evaluation: -1

The paper deals with the design of a FPGA implementing a subset of the MIL-1553B standard.

Unfortunately, the presentation of the work done by the authors stay at a very general level.
Hence, the reading of the paper has a limited interest.

In addition, there are many English mistakes making the paper difficult to read. The ideas are not clearly expressed. Please clarify them.

In Section I, the sentence starting with "Because the interfaces supported..." is not clear, please rephrase it.

In Section II, you should first explain the acronyms BC, RT and BM. You should then briefly present these three modes and better justify the choice of the RT mode. I do not understand the second paragraph, please rephrase it.
Please rephrase also The three last sentences of section II. I think that "discontinuity" is not the right term to use.

In Section III, in the second sentence what do you mean? Do you want to say that the number of remote terminals is higher than the number of any other device?

In Section III.C, you use "low technology dependability" as an advantage of your choice.High dependability is required. You use it again in the Conclusion.

In section IVD, what do you mean by "the message transmission ... is typically"? It should be compliant with the standard.


Review 2
Overall evaluation: -2

The paper proposes a new design for an FPGA-based MIL-STD-1553B RT subsystem, which is a field-bus for military applications. The advantages over previous designs seem to be the reduced costs, and hence the scalability. The proposed design has also been implemented as a prototype to validate the correctness and to analyze the real behaviour of the implementation. It has been shown that the prototype implementation indeed complies with the MIL-STD-1553B standard.

I am not well versed in the area of real-time networks, which made is quite cumbersome to read the paper. This problem was further amplified by the writing style and the lack of explanations. For instance, the authors assume that each and every reader is fully aware of what MIL-STD-1553 actually stands for. That it refers to a field-bus standard is not explained in the abstract, or in the conclusions. Since the authors assume a much higher proficiency in their domain than I have, I am not able to judge the correctness and consistency of their approach. Since I am convinced that I will not be alone with this problem at the conference, I believe the paper should be rejected.

Yet, also just by the writing of the paper, I vote to reject it. To get this paper accepted, the authors have to
- provide a much smoother introduction to their topic at a higher level. After all, it is a scientific conference, and low-level implementation details are not really interesting
- completely avoid Figure such as 3,4,6. There is nothing to be learnt from Figure 3, little to be learnt from Figure 4, and Figure 6 is not readable.
- improve the language. There are quite some strange grammatical constructions, which are not fully correct.


Review 3
Overall evaluation: -2

The paper is about implementation of a US military serial communication protocol using FPGA. The design adds also a CPU core to it.
The work is well written and structured.

About content: The scientific contribution is not clearly stated. Authors present an implementation proposal using FPGA. Is your proposal wiling to overcome some difficulties about implementation challenges?

Was the test bench created specifically for your development? Could you compare performance results among other running systems? What are the problems to overcome using your design proposal?

If you could change the direction of you work trying to answer those questions, then you are on the way of a scientific contribution.


Review 4
Overall evaluation: -2

There are several comments for this paper.

First, it is quite unusual for a WiP. It is somewhat of a work in progress, but this is not the typical structure for documenting work in progress, but the paper follows the conventional discussion of achieved results.

The problem is that the language is barely sufficient for understandability (it should be reviewed, there are several English errors) and contains several repetitions and vague statements.

The contributions seems marginal both in terms of novelty (an FPGA implementation of an MIL-STD-1553B controller) but especially in terms of design contributions. The system design is addressed only in its most simplistic way, no design challenges, options or issues are discussed, and the presented results consist only in electrical values as read by a logic analyzer.

In my opinion there is still a long way to go even for acceptance as WiP